2016-11-29 13:08:44 +01:00
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// See LICENSE for license details.
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package sifive.blocks.devices.xilinxvc707pciex1
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import Chisel._
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2017-07-23 17:31:44 +02:00
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import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
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2017-07-07 19:48:57 +02:00
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import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
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2016-11-29 13:08:44 +01:00
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2017-07-23 17:31:44 +02:00
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trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
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2016-11-29 13:08:44 +01:00
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val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
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2017-05-13 07:59:48 +02:00
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2017-07-23 17:31:44 +02:00
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sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
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xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
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xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
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ibus.fromAsync := xilinxvc707pcie.intnode
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2016-11-29 13:08:44 +01:00
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}
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2017-07-23 17:31:44 +02:00
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trait HasSystemXilinxVC707PCIeX1Bundle {
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2017-06-05 23:33:53 +02:00
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val xilinxvc707pcie: XilinxVC707PCIeX1IO
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def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
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pads <> xilinxvc707pcie
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}
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2016-11-29 13:08:44 +01:00
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}
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2017-07-23 17:31:44 +02:00
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trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
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with HasSystemXilinxVC707PCIeX1Bundle {
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val outer: HasSystemXilinxVC707PCIeX1
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2017-06-05 23:33:53 +02:00
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val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
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2016-11-29 13:08:44 +01:00
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2017-06-05 23:33:53 +02:00
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xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
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2017-05-13 07:59:48 +02:00
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outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
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2017-06-05 23:33:53 +02:00
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outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
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2016-11-29 13:08:44 +01:00
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}
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