Wesley W. Terpstra fa472e38fb tilelink2: monitor error line legality

2016-09-05 20:58:39 -07:00

..

Bases.scala

tilelink2: add an intermediate type for simple factories

2016-09-05 20:58:38 -07:00

Bundles.scala

tilelink2: document allowed (and required) response messages

2016-09-05 20:58:38 -07:00

GPIO.scala

tilelink2: connect abstract register-based modules to TileLink

2016-09-05 20:58:38 -07:00

Monitor.scala

tilelink2: monitor error line legality

2016-09-05 20:58:39 -07:00

Nodes.scala

tilelink2: assert-fail on something more user understandable

2016-09-05 20:58:38 -07:00

Operations.scala

tilelink2: move error from type into Bundle and add HintAck

2016-09-05 20:58:38 -07:00

Parameters.scala

tilelink2: transfers must never exceed 4kB

2016-09-05 20:58:38 -07:00

RegField.scala

tilelink2: support ready-valid enqueue+dequeue on register fields

2016-09-05 20:58:38 -07:00

RegisterRouter.scala

tilelink2: use consistent in/out ports for TLSimpleFactories

2016-09-05 20:58:38 -07:00

SRAM.scala

tilelink2: implement SRAM manager

2016-09-05 20:58:38 -07:00

Xbar.scala

tilelink2: add an intermediate type for simple factories

2016-09-05 20:58:38 -07:00