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debug_rom
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debug: Use flags for resume instead of program buffer. Untested.
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2017-04-07 16:47:16 -07:00 |
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.gitignore
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add makefile for float_fix and comlog tools
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2016-02-29 11:24:53 -08:00 |
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authors
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scripts/authors: Matthew Naylor's submissions were under Berkeley terms
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2016-11-27 22:15:43 -08:00 |
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check_cache_trace.py
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fix voluntary release issue in L2 cache
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2016-07-06 16:57:01 -07:00 |
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check_comparator_trace.py
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add a script for checking comparator trace
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2016-07-12 14:42:04 -07:00 |
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copyright-file
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scripts: two scripts to determine copyright holder of files
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2016-11-27 22:15:38 -08:00 |
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Makefile
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add makefile for float_fix and comlog tools
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2016-02-29 11:24:53 -08:00 |
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modify-copyright
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scripts: two scripts to determine copyright holder of files
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2016-11-27 22:15:38 -08:00 |
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RocketSim32.py
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debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN
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2018-01-05 16:10:13 -08:00 |
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RocketSim64.py
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debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN
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2018-01-05 16:10:13 -08:00 |
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RocketSim.cfg
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Debug regressions: Add necessary config scripts
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2018-01-05 16:03:59 -08:00 |
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RocketSim.py
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Debug regression: have to say something about memory in order to run a simple test
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2018-01-05 16:10:13 -08:00 |
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toaxe.py
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move groundtest/scripts to top-level scripts/
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2016-07-28 11:36:55 -07:00 |
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tracegen.py
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[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)
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2017-01-25 12:10:49 -08:00 |
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tracegen+check.sh
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get TraceGen working again
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2016-09-26 17:28:21 -07:00 |
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tracestats.py
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move groundtest/scripts to top-level scripts/
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2016-07-28 11:36:55 -07:00 |
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vlsi_mem_gen
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Avoid width warning
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2017-08-08 20:57:31 -07:00 |
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vlsi_rom_gen
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Change SystemVerilog statement into standard Verilog (#997)
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2017-09-18 10:57:07 -07:00 |
