Wesley W. Terpstra 8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051) ... We used to pack the addr_lo into user bits. We don't do that anymore. There is thus no need to waste those bits, nor to pass that arg.		2017-10-12 16:41:54 -07:00
..
BaseCoreplex.scala	Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars	2017-10-11 15:10:50 -07:00
Configs.scala	coreplex: move CacheCork in front of SBus	2017-10-10 16:24:32 -07:00
FrontBus.scala	coreplex: draw the FrontBus at the bottom and SystemBus at the top	2017-09-27 14:20:39 -07:00
InterruptBus.scala	diplomacy: change API to auto-create node bundles => cross-module refs	2017-09-22 15:01:39 -07:00
MemoryBus.scala	Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles	2017-09-27 16:28:10 -07:00
PeripheryBus.scala	coreplex: TileSlavePortParams inject adapters into PBus	2017-10-10 15:25:08 -07:00
Ports.scala	axi4: conversion from TL does not need beatBytes (#1051)	2017-10-12 16:41:54 -07:00
ResetVector.scala	tile: remove global Field ResetVectorBits	2017-09-08 14:50:59 -07:00
RocketCoreplex.scala	Merge pull request #1039 from freechipsproject/tile-crossing-params	2017-10-11 17:12:03 -07:00
RTC.scala	diplomacy: change API to auto-create node bundles => cross-module refs	2017-09-22 15:01:39 -07:00
SystemBus.scala	coreplex: TileMasterPortParams inject adapters into SBus	2017-10-10 15:02:50 -07:00