95 lines
2.1 KiB
Verilog
95 lines
2.1 KiB
Verilog
// See LICENSE for license details.
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//
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module ZscaleTestHarness;
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reg clk = 0;
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reg reset = 1;
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always #`CLOCK_PERIOD clk = ~clk;
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wire csr_resp_valid;
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wire [31:0] dummy;
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wire [31:0] csr_resp_bits;
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ZscaleTop dut
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(
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.clk(clk),
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.reset(reset),
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.io_host_reset(reset),
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.io_host_id(1'd0),
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.io_host_csr_req_ready(),
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.io_host_csr_req_valid(1'b1),
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.io_host_csr_req_bits_rw(1'b0),
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.io_host_csr_req_bits_addr(12'h780), // tohost register
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.io_host_csr_req_bits_data({dummy, 32'd0}),
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.io_host_csr_resp_ready(1'b1),
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.io_host_csr_resp_valid(csr_resp_valid),
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.io_host_csr_resp_bits({dummy, csr_resp_bits})
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);
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reg [1023:0] loadmem = 0;
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reg [1023:0] vcdplusfile = 0;
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reg [ 63:0] max_cycles = 0;
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reg [ 63:0] trace_count = 0;
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reg verbose = 0;
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integer stderr = 32'h80000002;
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integer i;
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reg [127:0] image [8191:0];
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initial
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begin
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$value$plusargs("max-cycles=%d", max_cycles);
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verbose = $test$plusargs("verbose");
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if ($value$plusargs("loadmem=%s", loadmem))
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begin
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$readmemh(loadmem, image);
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end
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if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
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begin
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$vcdplusfile(vcdplusfile);
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$vcdpluson(0);
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$vcdplusmemon(0);
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end
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#0.5;
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for (i=0; i<`BOOT_CAPACITY/16; i=i+1) begin
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dut.bootmem.ram.ram[4*i+0] = image[i][31:0];
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dut.bootmem.ram.ram[4*i+1] = image[i][63:32];
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dut.bootmem.ram.ram[4*i+2] = image[i][95:64];
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dut.bootmem.ram.ram[4*i+3] = image[i][127:96];
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end
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#777.7 reset = 0;
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end
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reg [255:0] reason = 0;
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always @(posedge clk)
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begin
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trace_count = trace_count + 1;
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if (max_cycles > 0 && trace_count > max_cycles)
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reason = "timeout";
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if (!reset)
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begin
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if (csr_resp_valid && csr_resp_bits > 1)
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$sformat(reason, "tohost = %d", csr_resp_bits >> 1);
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if (csr_resp_valid && csr_resp_bits == 1)
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begin
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$vcdplusclose;
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$finish;
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end
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end
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if (reason)
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begin
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$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
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$vcdplusclose;
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$finish;
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end
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end
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endmodule
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