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rocket-chip/vsrc
Palmer Dabbelt a0f3189c74 Change MIF_DATA_BITS back to 64
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
2016-02-27 11:43:44 -08:00
..
ZscaleTestHarness.v Remove IPI network 2015-11-16 21:53:14 -08:00
backup_mem.v Change MIF_DATA_BITS back to 64 2016-02-27 11:43:44 -08:00
rocketTestHarness.v Resurrect the backup memory port 2016-02-27 10:46:56 -08:00