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rocket-chip/src/main/scala
Wesley W. Terpstra 8ca6c10994 tilelink2: ToAXI4 can strip off low source ID bits
Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.

This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
2017-06-23 17:22:45 -07:00
..
config Configs: use a uniform syntax without Match exceptions (#507) 2017-01-13 14:41:19 -08:00
coreplex Move RoCC interface to Diplomacy and TL2 (#807) 2017-06-22 12:07:09 -07:00
diplomacy diplomacy: optimize IdRange.contains (#798) 2017-06-15 15:56:14 -07:00
groundtest groundtest: fix test ram width 2017-06-20 18:11:22 -07:00
jtag jtag: make it easier to assign MFR ID externally 2017-04-14 01:03:11 -07:00
junctions debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
regmapper ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00
rocket Move RoCC interface to Diplomacy and TL2 (#807) 2017-06-22 12:07:09 -07:00
rocketchip PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave 2017-06-13 16:59:29 -07:00
tile Move RoCC interface to Diplomacy and TL2 (#807) 2017-06-22 12:07:09 -07:00
uncore tilelink2: ToAXI4 can strip off low source ID bits 2017-06-23 17:22:45 -07:00
unittest unittest: balance the run times of the tests 2017-05-17 14:02:59 -07:00
util ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00