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riscv/rocket-chip
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e3c7bb3b1fbb46e5eff2322c9e618b45ec0b22e0
rocket-chip/src/main/scala
T
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Wesley W. TerpstraandGitHub e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835)
2017-06-29 19:07:12 -07:00
..
config
Configs: use a uniform syntax without Match exceptions (#507)
2017-01-13 14:41:19 -08:00
coreplex
diplomacy: add RWXC permissions also to ResourceMappings
2017-06-28 15:06:19 -07:00
diplomacy
diplomacy: a type of connect that always disables monitors (#828)
2017-06-28 21:48:10 -07:00
groundtest
groundtest: fix test ram width
2017-06-20 18:11:22 -07:00
jtag
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
junctions
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
regmapper
ReduceOthers: remove constants from the balanced AND tree
2017-06-23 00:28:05 -07:00
rocket
rocket: add dtim and itim refs to cpus
2017-06-28 23:10:58 -07:00
rocketchip
diplomacy: a type of connect that always disables monitors (#828)
2017-06-28 21:48:10 -07:00
tile
Move RoCC interface to Diplomacy and TL2 (#807)
2017-06-22 12:07:09 -07:00
uncore
SRAM: MemoryDevices use .reg (not .reg("mem")) (#835)
2017-06-29 19:07:12 -07:00
unittest
unittest: balance the run times of the tests
2017-05-17 14:02:59 -07:00
util
Add grouped method to AugmentedUInt, like Seq.grouped
2017-06-28 02:09:18 -07:00
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