..
AddressDecoder.scala
tilelink2 AddressDecoder: validate output of optimization
2016-09-16 16:09:00 -07:00
Arbiter.scala
tilelink2 Xbar: decouple ready from valid ( #338 )
2016-09-23 16:24:29 -07:00
AtomicAutomata.scala
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Buffer.scala
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Bundles.scala
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
Crossing.scala
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
Edges.scala
Tl2 addr width0 ( #346 )
2016-09-26 17:00:03 -07:00
Example.scala
RegMapper: regmap(...) now takes BYTE addresses
2016-09-22 20:52:46 -07:00
Fragmenter.scala
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Fuzzer.scala
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
HintHandler.scala
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
IntNodes.scala
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
Isolation.scala
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
LazyModule.scala
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
Legacy.scala
tilelink2 Legacy: convert TL1 atomic operand size
2016-09-22 15:18:54 -07:00
Monitor.scala
tilelink2 Monitor: work around for firrtl/verilator performance issue
2016-09-22 15:18:54 -07:00
Nodes.scala
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
package.scala
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Parameters.scala
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
RAMModel.scala
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00
RegField.scala
Move a bunch more things into util package
2016-09-29 14:23:42 -07:00
RegisterCrossing.scala
Suggest sane names for common objects ( #369 )
2016-09-30 16:19:25 -07:00
RegisterRouter.scala
tilelink2 RegisterRouter: minLatency is never more than 1
2016-09-22 15:51:15 -07:00
RegisterRouterTest.scala
[tilelink2] Add unit tests for many TL2 components
2016-09-28 18:02:04 -07:00
RegMapper.scala
tilelink2: don't use chisel3 namespace ( #355 )
2016-09-27 14:44:26 -07:00
SRAM.scala
[tilelink2] Add unit tests for many TL2 components
2016-09-28 18:02:04 -07:00
TLNodes.scala
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
WidthWidget.scala
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Xbar.scala
[tilelink2] Add unit tests for many TL2 components
2016-09-28 18:02:04 -07:00
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