118 lines
4.6 KiB
Scala
118 lines
4.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class PeripheryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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arithmeticAtomics: Boolean = true,
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bufferAtomics: BufferParams = BufferParams.default,
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sbusCrossingType: SubsystemClockCrossing = SynchronousCrossing(), // relative to sbus
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frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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) extends HasTLBusParams
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case object PeripheryBusKey extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams)
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(implicit p: Parameters) extends TLBusWrapper(params, "periphery_bus")
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with HasTLXbarPhy
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with HasCrossing {
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val crossing = params.sbusCrossingType
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def toSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= bufferTo(buffer) }
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}
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def toVariableWidthSlaveNode(name: Option[String] = None, buffer: BufferParams = BufferParams.none)(node: TLInwardNode) { toVariableWidthSlaveNodeOption(name, buffer)(Some(node)) }
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def toVariableWidthSlaveNodeOption(name: Option[String] = None, buffer: BufferParams = BufferParams.none)(node: Option[TLInwardNode]) {
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node foreach { n => to("slave" named name) { n :*= fragmentTo(buffer) } }
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}
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def toVariableWidthSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fragmentTo(buffer) }
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}
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def toFixedWidthSlaveNode(name: Option[String] = None, buffer: BufferParams = BufferParams.none)(gen: TLInwardNode) {
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to("slave" named name) { gen :*= fixedWidthTo(buffer) }
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}
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def toFixedWidthSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) { gen :*= fixedWidthTo(buffer) }
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}
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def toFixedWidthSingleBeatSlaveNode
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(widthBytes: Int, name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: TLInwardNode) {
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to("slave" named name) {
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gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
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}
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}
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def toFixedWidthSingleBeatSlave[D,U,E,B <: Data]
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(widthBytes: Int, name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) {
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gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
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}
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}
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def toLargeBurstSlave[D,U,E,B <: Data]
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(maxXferBytes: Int, name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("slave" named name) {
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gen :*= fragmentTo(params.beatBytes, maxXferBytes, buffer)
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}
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}
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def toFixedWidthPort[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] =
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TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = {
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to("port" named name) { gen := fixedWidthTo(buffer) }
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}
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def fromSystemBus(gen: => TLOutwardNode) {
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from("sbus") {
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(inwardNode
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:*= TLBuffer(params.bufferAtomics)
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:*= TLAtomicAutomata(arithmetic = params.arithmeticAtomics)
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:*= gen)
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}
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}
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def fromOtherMaster[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
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TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
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from("master" named name) { bufferFrom(buffer) :=* gen }
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}
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def toTile
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(name: Option[String] = None, buffers: Int = 0)
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(gen: => TLNode): TLOutwardNode = {
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to("tile" named name) { FlipRendering { implicit p =>
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gen :*= bufferTo(buffers)
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}}
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}
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}
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