1
0
rocket-chip/src/main/scala
Andrew Waterman c6135a02df Revert "rocket: hard-wire UXL/SXL fields to 0"
This reverts commit ea0714bfcb.

We've waffled on this matter in the priv spec: 326bec83de
2017-05-07 15:23:21 -07:00
..
config Configs: use a uniform syntax without Match exceptions (#507) 2017-01-13 14:41:19 -08:00
coreplex axi4: ToTL supporting pipelined MMIO 2017-05-01 22:53:40 -07:00
diplomacy diplomacy: optimize IdRange overlap detection 2017-05-01 22:53:41 -07:00
groundtest Fix regression in groundtest DummyPTW 2017-03-28 00:56:14 -07:00
jtag jtag: make it easier to assign MFR ID externally 2017-04-14 01:03:11 -07:00
junctions debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
regmapper regmapper: remove the Pipe in the RegMapper Queue 2017-04-19 21:37:37 -07:00
rocket Revert "rocket: hard-wire UXL/SXL fields to 0" 2017-05-07 15:23:21 -07:00
rocketchip rocketchip: move the Error device to 0x3000 2017-05-01 22:53:41 -07:00
tile local_interrupts: Correct off-by-1 if there is no SEIP 2017-05-02 21:55:25 -07:00
uncore Wes fix for AXI2TL timeout when writes backed up 2017-05-04 00:54:21 -07:00
unittest unittest: put AtomicAutomata under regression 2017-04-14 15:13:39 -07:00
util Support indexing 1-entry Seqs 2017-04-26 19:35:35 -07:00