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rocket-chip/vsrc/plusarg_reader.v
Shreesha Srinath ff1f0170dc changing SystemVerilog params to Verilog style (#801)
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
2017-06-16 22:47:12 -07:00

21 lines
494 B
Verilog

// See LICENSE.SiFive for license details.
// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
// but Incisive demands them. These default values should never be used.
module plusarg_reader #(FORMAT="borked=%d", DEFAULT=0) (
output [31:0] out
);
reg [31:0] myplus;
assign out = myplus;
initial begin
`ifdef SYNTHESIS
myplus = DEFAULT;
`else
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
`endif
end
endmodule