Henry Cook b7730d66f2 WIP bugfixes: run until corrupted WB data (beats repeated)

2016-11-11 18:34:48 -08:00

..

coreplex

WIP scala compile and firrtl elaborate; monitor error

2016-11-11 13:07:45 -08:00

diplomacy

tilelink2 Xbar: merge the AddressSets of fractured managers

2016-11-03 22:18:28 -07:00

groundtest

WIP scala compile and firrtl elaborate; monitor error

2016-11-11 13:07:45 -08:00

junctions

rocketchip: all of the address map now comes from TL2

2016-10-31 11:42:44 -07:00

regmapper

regmapper RegisterCrossing: safe AsyncQueues are overkill here

2016-10-14 18:28:31 -07:00

rocket

WIP bugfixes: run until corrupted WB data (beats repeated)

2016-11-11 18:34:48 -08:00

rocketchip

rocketchip: use TL2 and AXI4 for memory subsytem

2016-11-04 13:36:47 -07:00

uncore

WIP bugfixes: run until corrupted WB data (beats repeated)

2016-11-11 18:34:48 -08:00

unittest

diplomacy: print out bus widths on edges in agent graph

2016-10-31 11:42:47 -07:00

util

WIP uncore and rocket changes compile

2016-11-10 15:57:29 -08:00