1
0
rocket-chip/vsim
Wesley W. Terpstra 91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs)
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
2017-02-17 14:26:23 +01:00
..
.gitignore Write test harness in Chisel 2016-08-15 23:27:27 -07:00
Makefile Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Makefrag ClockDivider2: fix launch alignment of clocks (vcs) 2017-02-17 14:26:23 +01:00
Makefrag-verilog Artefact output (#545) 2017-02-02 19:24:55 -08:00
vlsi_mem_gen Perform integer division when parsing rocketchip.DefaultConfig.conf (#493) 2017-01-13 16:40:02 -08:00