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riscv/rocket-chip
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8c4ac0f4f341a245221582bb9d3fd98cb84c4da6
rocket-chip/uncore/src/main/scala
T
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Howard Mao 8c4ac0f4f3 make sure CSR/SCR data width matches xLen
2015-09-25 12:07:03 -07:00
..
broadcast.scala
use Put/Get/PutBlock/GetBlock constructors in broadcast hub
2015-09-14 12:57:54 -07:00
cache.scala
replace remaining uses of Vec.fill
2015-09-24 17:50:09 -07:00
coherence.scala
make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper
2015-09-14 12:57:54 -07:00
consts.scala
Chisel3 compatibility: use BitPat for don't-cares
2015-07-28 02:46:23 -07:00
directory.scala
First pages commit
2015-04-29 13:18:26 -07:00
ecc.scala
Chisel3 compatibility: use >>Int instead of >>UInt
2015-08-04 13:15:17 -07:00
htif.scala
make sure CSR/SCR data width matches xLen
2015-09-25 12:07:03 -07:00
metadata.scala
Add Wire() wrap
2015-07-15 20:24:03 -07:00
network.scala
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:47:02 -07:00
package.scala
First pages commit
2015-04-29 13:18:26 -07:00
rtc.scala
make sure CSR/SCR data width matches xLen
2015-09-25 12:07:03 -07:00
scr.scala
split off SCR functionality from HTIF
2015-09-14 12:57:54 -07:00
tilelink.scala
ReorderQueue uses Vec of Bools instead of Bits for roq_free
2015-09-24 17:43:53 -07:00
uncore.scala
fix broadcast hub and TL -> NASTI converter to support subblock operations
2015-09-14 12:56:44 -07:00
util.scala
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:47:02 -07:00
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