Wesley W. Terpstra 36f4584bb1 axi4: Test AXI4-Lite in regression		2017-05-08 00:31:35 -07:00
..
Buffer.scala	axi4: use common BufferParams	2017-03-16 15:32:17 -07:00
Bundles.scala	AXI4: add an optional user bundle field	2017-05-01 22:53:01 -07:00
Deinterleaver.scala	axi4: Deinterleaver must gather R also for single ID	2017-05-08 00:17:06 -07:00
Fragmenter.scala	axi4: Fragmenter cuts all input channel readys	2017-05-01 22:53:41 -07:00
IdIndexer.scala	axi4: IdIndexer; a single ID does NOT imply no response interleaving	2017-05-08 00:17:06 -07:00
Nodes.scala	diplomacy: use HeterogeneousBag instead of Vec	2017-02-22 17:05:22 -08:00
package.scala	copyright: ran scripts/modify-copyright	2016-11-27 22:15:43 -08:00
Parameters.scala	axi4: IdIndexer; a single ID does NOT imply no response interleaving	2017-05-08 00:17:06 -07:00
Protocol.scala	rocketchip: work-around ucb-bar/chisel3#472	2017-01-31 14:20:02 -08:00
RegisterRouter.scala	axi4: RegisterRouter; concurrent response illegal in AXI	2017-05-01 22:53:01 -07:00
SRAM.scala	axi4: SRAM support 0 userBits	2017-05-08 00:31:14 -07:00
Test.scala	axi4: Test AXI4-Lite in regression	2017-05-08 00:31:35 -07:00
ToTL.scala	Wes fix for AXI2TL timeout when writes backed up	2017-05-04 00:54:21 -07:00
UserYanker.scala	axi4: make maxFlight a per-master parameter	2017-05-01 22:53:40 -07:00