riscv/rocket-chip
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rocket-chip/src/main/scala/tile
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Henry Cook b625e68360
tile: put a BasicBusBlocker inside RocketTile (#1115) 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
2017-11-17 17:26:48 -08:00
..
BaseTile.scala
tile: put a BasicBusBlocker inside RocketTile (#1115)
2017-11-17 17:26:48 -08:00
Core.scala
Provide option to support AMOs only on I/O, not DTIM/D$
2017-11-09 17:45:53 -08:00
FPU.scala
FPU : simplify pipeline register generation in FMA
2017-10-05 15:18:19 -07:00
Interrupts.scala
IntNodes: moved from tilelink to their own package
2017-10-25 16:56:51 -07:00
L1Cache.scala
tile: remove PAddrBits in favor of SharedMemoryTLEdge
2017-09-08 13:53:36 -07:00
LazyRoCC.scala
diplomacy: define only primary node types
2017-10-28 11:16:56 -07:00
RocketTile.scala
tile: put a BasicBusBlocker inside RocketTile (#1115)
2017-11-17 17:26:48 -08:00