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rocket-chip/src/main/scala/tile/L1Cache.scala

50 lines
1.5 KiB
Scala

// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import Chisel._
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.tilelink.ClientMetadata
import freechips.rocketchip.util._
trait L1CacheParams {
def nSets: Int
def nWays: Int
def rowBits: Int
def nTLBEntries: Int
def blockBytes: Int
}
trait HasL1CacheParameters {
implicit val p: Parameters
val cacheParams: L1CacheParams
private val bundleParams = p(SharedMemoryTLEdge).bundle
def cacheBlockBytes = cacheParams.blockBytes
def lgCacheBlockBytes = log2Up(cacheBlockBytes)
def nSets = cacheParams.nSets
def blockOffBits = lgCacheBlockBytes
def idxBits = log2Up(cacheParams.nSets)
def untagBits = blockOffBits + idxBits
def tagBits = bundleParams.addressBits - untagBits
def nWays = cacheParams.nWays
def wayBits = log2Up(nWays)
def isDM = nWays == 1
def rowBits = cacheParams.rowBits
def rowBytes = rowBits/8
def rowOffBits = log2Up(rowBytes)
def nTLBEntries = cacheParams.nTLBEntries
def cacheDataBits = bundleParams.dataBits
def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits
def refillCycles = cacheDataBeats
}
abstract class L1CacheModule(implicit val p: Parameters) extends Module
with HasL1CacheParameters
abstract class L1CacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasL1CacheParameters