85 lines
3.1 KiB
Scala
85 lines
3.1 KiB
Scala
package Top {
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import Chisel._;
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import Node._;
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import Constants._;
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import scala.math._;
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class ioIPrefetcher extends Bundle() {
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val icache = new ioDCache();
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val mem = new ioDCache().flip()
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val invalidate = Bool(INPUT)
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}
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class rocketIPrefetcher extends Component() {
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val io = new ioIPrefetcher();
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val pdq = (new queue(REFILL_CYCLES, flushable = true)) { Bits(width = MEM_DATA_BITS) };
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val s_invalid :: s_valid :: s_refilling :: s_req_wait :: s_resp_wait :: s_bad_resp_wait :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_invalid);
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val demand_miss = io.icache.req_val & io.icache.req_rdy;
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val prefetch_addr = Reg() { UFix(width = io.icache.req_addr.width) };
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when (demand_miss) { prefetch_addr := io.icache.req_addr + UFix(1); }
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val addr_match = (prefetch_addr === io.icache.req_addr);
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val hit = (state != s_invalid) & (state != s_req_wait) & addr_match;
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io.icache.req_rdy := io.mem.req_rdy;
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val ip_mem_req_rdy = io.mem.req_rdy & ~(io.icache.req_val & ~hit);
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val ip_mem_resp_val = io.mem.resp_val && io.mem.resp_tag(0).toBool;
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io.mem.req_val := io.icache.req_val & ~hit | (state === s_req_wait);
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io.mem.req_rw := Bool(false)
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io.mem.req_tag := Mux(io.icache.req_val && !hit, UFix(0), UFix(1))
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io.mem.req_addr := Mux(io.mem.req_tag(0).toBool, prefetch_addr, io.icache.req_addr);
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val fill_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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when (ip_mem_resp_val.toBool) { fill_cnt := fill_cnt + UFix(1); }
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val fill_done = (~fill_cnt === UFix(0)) & ip_mem_resp_val;
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val forward = Reg(resetVal = Bool(false));
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val forward_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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when (forward & pdq.io.deq.valid) { forward_cnt := forward_cnt + UFix(1); }
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val forward_done = (~forward_cnt === UFix(0)) & pdq.io.deq.valid;
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forward := (demand_miss & hit | forward & ~forward_done);
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io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag(0).toBool) || (forward && pdq.io.deq.valid);
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io.icache.resp_data := Mux(forward, pdq.io.deq.bits, io.mem.resp_data);
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pdq.io.flush := Reg(demand_miss && !hit || (state === s_bad_resp_wait), resetVal = Bool(false))
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pdq.io.enq.bits := io.mem.resp_data;
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pdq.io.enq.valid := ip_mem_resp_val.toBool;
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pdq.io.deq.ready := forward;
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switch (state) {
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is (s_invalid) {
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when (demand_miss) { state := s_req_wait; }
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}
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is (s_valid) {
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when (demand_miss | (forward & forward_done)) { state := s_req_wait; }
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}
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is (s_refilling) {
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when (demand_miss & ~addr_match & fill_done.toBool) { state := s_req_wait; }
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.elsewhen (demand_miss & ~addr_match) { state := s_bad_resp_wait; }
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.elsewhen (fill_done.toBool) { state := s_valid; }
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}
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is (s_req_wait) {
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when (ip_mem_req_rdy) { state := s_resp_wait; }
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}
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is (s_resp_wait) {
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when (demand_miss & ~addr_match) { state := s_bad_resp_wait; }
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.elsewhen (ip_mem_resp_val.toBool) { state := s_refilling; }
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}
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is (s_bad_resp_wait) {
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when (fill_done.toBool & ip_mem_resp_val.toBool) { state := s_req_wait; }
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}
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}
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when (io.invalidate) {
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state := s_invalid
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}
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}
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}
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