| .. |
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arbiter.scala
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
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coherence.scala
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finished xact_finish and xact_abort transactors in coherence hub
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2012-02-23 18:12:50 -08:00 |
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consts.scala
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Improved TileIO organization, beginnings of hub implementation
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2012-02-22 18:24:52 -08:00 |
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cpu.scala
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expose FMA ports outside of FPU (for the VU)
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2012-02-23 17:39:34 -08:00 |
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ctrl_util.scala
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parameterize the scoreboards
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2012-02-13 18:12:23 -08:00 |
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ctrl_vec.scala
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bug fixes to ctrl_vec
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2012-02-23 22:35:05 -08:00 |
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ctrl.scala
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fix ctrl vec iface hookup - final
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2012-02-23 23:03:44 -08:00 |
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divider.scala
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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dpath_alu.scala
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new build system with updated chisel, hwacha
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2012-02-14 19:43:59 -08:00 |
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dpath_util.scala
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new htif protocol and implementation
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2012-02-19 23:15:45 -08:00 |
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dpath_vec.scala
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fix bug in rocket's vector datapath related to wakeup
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2012-02-23 10:14:14 -08:00 |
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dpath.scala
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move datapath control signals into control unit
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2012-02-23 16:52:52 -08:00 |
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dtlb.scala
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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fpu.scala
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expose FMA ports outside of FPU (for the VU)
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2012-02-23 17:39:34 -08:00 |
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htif.scala
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fix fpga build
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2012-02-23 22:19:38 -08:00 |
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icache_prefetch.scala
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
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icache.scala
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
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instructions.scala
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new mftx instruction format
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2011-12-12 03:23:12 -08:00 |
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itlb.scala
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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multiplier.scala
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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nbdcache.scala
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allocate a primary miss on a prefetch
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2012-02-23 22:40:24 -08:00 |
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ptw.scala
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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queues.scala
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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top.scala
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HTIF now controls CPU reset
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2012-02-22 19:30:03 -08:00 |
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util.scala
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declaring success on FPU for now
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2012-02-14 19:11:57 -08:00 |
