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rocket-chip/src/main/scala
2017-08-05 14:22:40 -07:00
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amba tilelink: Error device supports Acquire 2017-07-27 18:32:58 -07:00
config Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
coreplex tilelink: add mask rom 2017-07-31 21:34:04 -07:00
devices tilelink: add mask rom 2017-07-31 21:34:04 -07:00
diplomacy diplomacy: Pretty Print for TransferSizes 2017-08-02 11:40:50 -07:00
groundtest chiplink: adjust bus view to include the splitter (#886) 2017-07-24 21:41:17 -07:00
jtag Use chisel3 Clock() method. 2017-07-07 14:16:39 -07:00
regmapper add cloneType to RegisterWriteIO and RegisterReadIO (#874) 2017-07-18 18:52:31 -07:00
rocket Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00
system tilelink: add mask rom 2017-07-31 21:34:04 -07:00
tile Use 1-entry queue on processor-side E-channel 2017-07-31 18:06:54 -07:00
tilelink TLXbar: Allow more masters and slaves and issue a warning. 2017-08-03 15:46:06 -07:00
unittest Combine Coreplex and System Module Hierarchies (#875) 2017-07-23 08:31:04 -07:00
util Optimize ShiftQueue for late-arriving deq.ready 2017-08-04 22:06:37 -07:00