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rocket-chip/rocket/src/main/scala
2011-11-14 01:37:20 -08:00
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arbiter.scala more itlb integration & cleanup 2011-11-09 23:18:14 -08:00
consts.scala synced up with supervisor mode state in latest ISA simulator 2011-11-14 01:37:20 -08:00
cpu.scala added ld/st misaligned exceptions 2011-11-13 00:03:17 -08:00
ctrl_util.scala initial commit of rocket chisel project, riscv assembly tests and benchmarks 2011-10-25 23:02:47 -07:00
ctrl.scala more cache fixes, more test harness debug output 2011-11-13 23:32:18 -08:00
dcache.scala more cache fixes, more test harness debug output 2011-11-13 23:32:18 -08:00
divider.scala initial commit of rocket chisel project, riscv assembly tests and benchmarks 2011-10-25 23:02:47 -07:00
dpath_alu.scala more itlb integration & cleanup 2011-11-09 23:18:14 -08:00
dpath_util.scala synced up with supervisor mode state in latest ISA simulator 2011-11-14 01:37:20 -08:00
dpath.scala synced up with supervisor mode state in latest ISA simulator 2011-11-14 01:37:20 -08:00
dtlb.scala more cache fixes, more test harness debug output 2011-11-13 23:32:18 -08:00
icache_prefetch.scala more itlb integration & cleanup 2011-11-09 23:18:14 -08:00
icache.scala cache optimizations, cleanup, and testharness improvement 2011-11-12 22:13:29 -08:00
instructions.scala regenerated instruction encodings using parse-opcodes 2011-11-13 00:59:02 -08:00
itlb.scala more cache fixes, more test harness debug output 2011-11-13 23:32:18 -08:00
multiplier.scala initial commit of rocket chisel project, riscv assembly tests and benchmarks 2011-10-25 23:02:47 -07:00
ptw.scala more itlb/dtlb/ptw fixes 2011-11-12 15:00:45 -08:00
queues.scala initial commit of rocket chisel project, riscv assembly tests and benchmarks 2011-10-25 23:02:47 -07:00
top.scala integrating ITLB & PTW 2011-11-09 14:52:17 -08:00
util.scala cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB 2011-11-10 11:26:13 -08:00