ff1f0170dc
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters |
||
---|---|---|
.. | ||
AsyncResetReg.v | ||
ClockDivider2.v | ||
ClockDivider3.v | ||
jtag_vpi.tab | ||
jtag_vpi.v | ||
plusarg_reader.v | ||
SimDTM.v | ||
TestDriver.v |
ff1f0170dc
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters |
||
---|---|---|
.. | ||
AsyncResetReg.v | ||
ClockDivider2.v | ||
ClockDivider3.v | ||
jtag_vpi.tab | ||
jtag_vpi.v | ||
plusarg_reader.v | ||
SimDTM.v | ||
TestDriver.v |