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riscv/rocket-chip
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58a4529cc52aec640e85a75f3b9c7e4839f73db3
rocket-chip/src/main/scala
T
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Wesley W. Terpstra 58a4529cc5 axi4: the last missing piece for safe FIFO ordering
2017-05-01 22:53:41 -07:00
..
config
Configs: use a uniform syntax without Match exceptions (#507)
2017-01-13 14:41:19 -08:00
coreplex
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
diplomacy
diplomacy: optimize IdRange overlap detection
2017-05-01 22:53:41 -07:00
groundtest
Fix regression in groundtest DummyPTW
2017-03-28 00:56:14 -07:00
jtag
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
junctions
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
regmapper
regmapper: remove the Pipe in the RegMapper Queue
2017-04-19 21:37:37 -07:00
rocket
rocket: turn on early ack for DTIM
2017-05-01 22:53:41 -07:00
rocketchip
rocketchip: move the Error device to 0x3000
2017-05-01 22:53:41 -07:00
tile
Interrupts: Less Pessimistic Synchronization (#714)
2017-04-28 14:49:24 -07:00
uncore
axi4: the last missing piece for safe FIFO ordering
2017-05-01 22:53:41 -07:00
unittest
unittest: put AtomicAutomata under regression
2017-04-14 15:13:39 -07:00
util
Support indexing 1-entry Seqs
2017-04-26 19:35:35 -07:00
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