| .. |
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ALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AMOALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Breakpoint.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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BTB.scala
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Fix BTB not being refilled on some indirect jumps
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2017-07-26 02:13:43 -07:00 |
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Consts.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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CSR.scala
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Remove redundant check in interrupt priority encoding
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2017-08-17 22:23:42 -07:00 |
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DCache.scala
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Don't permit new acquires until the release queue is drained
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2017-08-13 13:18:45 -07:00 |
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Decode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Events.scala
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Add method to print perf events
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2017-07-25 15:19:16 -07:00 |
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Frontend.scala
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Make I vs. D a static property of TLB, not an input pin
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2017-08-08 11:54:47 -07:00 |
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HellaCache.scala
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Add option to retime D$ way mux into subsequent pipeline stage
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2017-08-01 23:59:20 -07:00 |
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HellaCacheArbiter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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IBuf.scala
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Roll back use of UIntToOH1 (#946)
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2017-08-09 18:39:47 -07:00 |
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ICache.scala
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Separate I$ parity error from miss signal
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2017-08-04 16:59:21 -07:00 |
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IDecode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Instructions.scala
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Add RVC instruction patterns
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2017-07-25 15:19:16 -07:00 |
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Multiplier.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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NBDcache.scala
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Make I vs. D a static property of TLB, not an input pin
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2017-08-08 11:54:47 -07:00 |
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package.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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PMP.scala
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Use UIntToOH1 (#921)
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2017-08-03 14:55:39 -07:00 |
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PTW.scala
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Get L2 TLB tag/parity check off the D$ arbitration path
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2017-08-04 17:01:51 -07:00 |
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RocketCore.scala
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max-core-cycles: Add a +max-core-cycles PlusArg
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2017-08-13 15:47:14 -07:00 |
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RVC.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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ScratchpadSlavePort.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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SimpleHellaCacheIF.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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TLB.scala
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Don't report to the DTIM that data is cacheable
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2017-08-08 11:55:04 -07:00 |
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TLBPermissions.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
