84 lines
3.3 KiB
Scala
84 lines
3.3 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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import Util._
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case class RocketConfiguration(tl: TileLinkConfiguration, as: AddressSpaceConfiguration,
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icache: ICacheConfig, dcache: DCacheConfig,
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rocc: Option[RocketConfiguration => RoCC] = None,
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retireWidth: Int = 1,
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vm: Boolean = true,
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fastLoadWord: Boolean = true,
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fastLoadByte: Boolean = false,
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fastMulDiv: Boolean = true)
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{
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val dcacheReqTagBits = 7 // enforce compliance with require()
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val xprlen = 64
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val nxpr = 32
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val nxprbits = log2Up(nxpr)
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if (fastLoadByte) require(fastLoadWord)
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}
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal)
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{
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val memPorts = 2 + (!confIn.rocc.isEmpty).toInt // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc
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val dcachePortId = 0
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val icachePortId = 1
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val roccPortId = 2
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val dcachePorts = 2 + (!confIn.rocc.isEmpty).toInt // Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC
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implicit val tlConf = confIn.tl
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implicit val lnConf = confIn.tl.ln
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implicit val icConf = confIn.icache
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implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(dcachePorts), databits = confIn.xprlen)
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implicit val conf = confIn.copy(dcache = dcConf)
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require(conf.retireWidth == 1) // for now...
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val io = new Bundle {
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val tilelink = new TileLinkIO
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val host = new HTIFIO(lnConf.nClients)
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}
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val core = Module(new Core)
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val icache = Module(new Frontend)
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val dcache = Module(new HellaCache)
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val ptw = Module(new PTW(if (confIn.rocc.isEmpty) 2 else 5)) // 2 ports, 1 from I$, 1 from D$, maybe 3 from RoCC
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val dcacheArb = Module(new HellaCacheArbiter(dcachePorts))
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dcacheArb.io.requestor(0) <> ptw.io.mem
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dcacheArb.io.requestor(1) <> core.io.dmem
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dcache.io.cpu <> dcacheArb.io.mem
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ptw.io.requestor(0) <> icache.io.cpu.ptw
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ptw.io.requestor(1) <> dcache.io.cpu.ptw
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core.io.host <> io.host
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core.io.imem <> icache.io.cpu
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core.io.ptw <> ptw.io.dpath
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val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts))
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memArb.io.in(dcachePortId) <> dcache.io.mem
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memArb.io.in(icachePortId) <> icache.io.mem
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if (!conf.rocc.isEmpty) {
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val rocc = Module((conf.rocc.get)(conf))
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val dcIF = Module(new SimpleHellaCacheIF)
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dcIF.io.requestor <> rocc.io.mem
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core.io.rocc <> rocc.io
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dcacheArb.io.requestor(2) <> dcIF.io.cache
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memArb.io.in(roccPortId) <> rocc.io.imem
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ptw.io.requestor(2) <> rocc.io.iptw
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ptw.io.requestor(3) <> rocc.io.dptw
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ptw.io.requestor(4) <> rocc.io.pptw
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}
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io.tilelink.acquire <> memArb.io.out.acquire
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memArb.io.out.grant <> io.tilelink.grant
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io.tilelink.finish <> memArb.io.out.finish
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dcache.io.mem.probe <> io.tilelink.probe
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io.tilelink.release.valid := dcache.io.mem.release.valid
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dcache.io.mem.release.ready := io.tilelink.release.ready
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io.tilelink.release.bits := dcache.io.mem.release.bits
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io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
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}
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