Jack Koenig 64b707cbb6 Bump Chisel and FIRRTL for annotations refactor (#1261) ...

Also brings in an autoclonetype enhancement and some bug fixes

2018-03-07 10:22:38 -08:00

..

.gitignore

Write test harness in Chisel

2016-08-15 23:27:27 -07:00

Makefile

Use vlsi_mem_gen for verilator flow

2017-08-07 20:36:22 -07:00

Makefrag

Remove JTAG vpi from VCS build

2018-02-26 15:12:18 -05:00

Makefrag-verilog

Bump Chisel and FIRRTL for annotations refactor (#1261)

2018-03-07 10:22:38 -08:00