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rocket-chip/src/main/scala/coreplex
Megan Wachs df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655)
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
..
BaseCoreplex.scala rocket: use diplomatic interrupts 2017-03-02 21:19:23 -08:00
Configs.scala debug: Make it easier to override parts of the Default Debug Config (#655) 2017-04-06 10:33:17 -07:00
Coreplex.scala rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
CoreplexNetwork.scala soc: compatible with "simple-bus" => scanned for platform devices 2017-03-30 00:36:23 -07:00
RISCVPlatform.scala debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
RocketTiles.scala Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00