82 lines
2.7 KiB
Scala
82 lines
2.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package coreplex
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import Chisel._
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import config._
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import diplomacy._
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import tile.XLen
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import tile.TileInterrupts
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import uncore.tilelink2._
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import util._
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/** Widths of various points in the SoC */
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case class TLBusConfig(beatBytes: Int)
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case object CBusConfig extends Field[TLBusConfig]
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case object L1toL2Config extends Field[TLBusConfig]
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// These parameters apply to all caches, for now
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case object CacheBlockBytes extends Field[Int]
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/** L2 Broadcast Hub configuration */
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case class BroadcastConfig(
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nTrackers: Int = 4,
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bufferless: Boolean = false)
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case object BroadcastConfig extends Field[BroadcastConfig]
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/** L2 memory subsystem configuration */
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case class BankedL2Config(
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nMemoryChannels: Int = 1,
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nBanksPerChannel: Int = 1,
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coherenceManager: (Parameters, CoreplexNetwork) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
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implicit val p = q
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val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
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val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
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val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
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ww.node :*= bh.node
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(bh.node, ww.node)
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}) {
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val nBanks = nMemoryChannels*nBanksPerChannel
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}
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case object BankedL2Config extends Field[BankedL2Config]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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trait HasCoreplexParameters {
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implicit val p: Parameters
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lazy val tilesParams = p(RocketTilesKey)
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lazy val cbusConfig = p(CBusConfig)
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lazy val l1tol2Config = p(L1toL2Config)
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lazy val nTiles = tilesParams.size
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lazy val l2Config = p(BankedL2Config)
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}
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope
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abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexNetwork
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with BankedL2CoherenceManagers {
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override lazy val module = new BaseCoreplexModule(this, () => new BaseCoreplexBundle(this))
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}
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class BaseCoreplexBundle[+L <: BaseCoreplex](_outer: L) extends BareCoreplexBundle(_outer)
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with CoreplexNetworkBundle
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with BankedL2CoherenceManagersBundle
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class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](_outer: L, _io: () => B) extends BareCoreplexModule(_outer, _io)
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with CoreplexNetworkModule
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with BankedL2CoherenceManagersModule
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