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rocket-chip/vsim
Schuyler Eldridge 8bb397a1b9 Fix VCS argument parsing (#1266)
* Add +permissive/+permissive-off for VCS args

This adds guards around Verilog/VCS options for VCS calls with HTIF's
new `+permissive`/`+permissive-off` options. This enables HTIF to
permissively parse all options inside one of these guards while not
erroring on unknonw commands. This is necessary for VCS, unlike with the
emulator, as HTIF is giving all commands as opposed to only host and
target arguments (like with Verilator/emulator.cc).

* Bump riscv-tools for fesvr VCS fix

* Bump riscv-rools/riscv-fesvr (VCS stderr fix)

Fixes #1266

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-07 22:59:04 -08:00
..
.gitignore Write test harness in Chisel 2016-08-15 23:27:27 -07:00
Makefile Use vlsi_mem_gen for verilator flow 2017-08-07 20:36:22 -07:00
Makefrag Fix VCS argument parsing (#1266) 2018-03-07 22:59:04 -08:00
Makefrag-verilog Fix VCS argument parsing (#1266) 2018-03-07 22:59:04 -08:00