8bb397a1b9
* Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
54 lines
2.6 KiB
Plaintext
54 lines
2.6 KiB
Plaintext
#--------------------------------------------------------------------
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# Verilog Generation
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#--------------------------------------------------------------------
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firrtl = $(generated_dir)/$(long_name).fir
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verilog = $(generated_dir)/$(long_name).v
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# If I don't mark these as .SECONDARY then make will delete these internal
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# files.
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.SECONDARY: $(firrtl) $(verilog)
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$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno.json
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
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cd $(generated_dir) && \
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rm -f $@ && \
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$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
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mv $@.tmp $@
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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.PRECIOUS: $(output_dir)/%.vpd
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$(output_dir)/%.run: $(output_dir)/% $(simv)
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cd $(sim_dir) && $(exec_simv) +permissive +max-cycles=$(timeout_cycles) +permissive-off $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.out: $(output_dir)/% $(simv)
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cd $(sim_dir) && $(exec_simv) +permissive +verbose +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vcd: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +permissive +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && $(exec_simv_debug) +permissive +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
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$(output_dir)/%.saif: $(output_dir)/% $(simv_debug)
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cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +permissive +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) +permissive-off $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
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run: run-asm-tests run-bmark-tests
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run-debug: run-asm-tests-debug run-bmark-tests-debug
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run-fast: run-asm-tests-fast run-bmark-tests-fast
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.PHONY: run-asm-tests run-bmark-tests
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.PHONY: run-asm-tests-debug run-bmark-tests-debug
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.PHONY: run run-debug run-fast
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junk += $(output_dir)
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