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rocket-chip/vsim
Megan Wachs e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
..
.gitignore Write test harness in Chisel 2016-08-15 23:27:27 -07:00
Makefile Use vlsi_mem_gen for verilator flow 2017-08-07 20:36:22 -07:00
Makefrag Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. 2018-01-05 16:02:52 -08:00
Makefrag-verilog Bump chisel3 and firrtl and bump sbt to version 1.0.4 2017-12-18 12:09:21 -08:00