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riscv/rocket-chip
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183fefb2b9d424f7ab9085b53996bfc57a7743d5
rocket-chip/src/main/scala
T
History
Megan Wachs 183fefb2b9 Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
..
amba
tilelink: Error device supports Acquire
2017-07-27 18:32:58 -07:00
config
Refactor package hierarchy and remove legacy bus protocol implementations (#845)
2017-07-07 10:48:16 -07:00
coreplex
Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
devices
SystemBus: use a full buffer on slaves
2017-08-26 02:47:04 -07:00
diplomacy
TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.
2017-08-29 10:36:46 -07:00
groundtest
chiplink: adjust bus view to include the splitter (#886)
2017-07-24 21:41:17 -07:00
jtag
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
regmapper
add cloneType to RegisterWriteIO and RegisterReadIO (#874)
2017-07-18 18:52:31 -07:00
rocket
Remove redundant check in interrupt priority encoding
2017-08-17 22:23:42 -07:00
system
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
tile
Fixing requirements for PAddrBits (#961)
2017-08-17 11:53:59 -07:00
tilelink
TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.
2017-08-29 10:36:46 -07:00
unittest
Combine Coreplex and System Module Hierarchies (#875)
2017-07-23 08:31:04 -07:00
util
HeterogenousBag: empty bags were being combined! (#956)
2017-08-14 15:48:42 -07:00
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