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rocket-chip/src/main/scala
Megan Wachs 0668f13d99 debug: Fix race between resumereq and resumeack
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
2017-06-29 12:27:23 -07:00
..
config Configs: use a uniform syntax without Match exceptions (#507) 2017-01-13 14:41:19 -08:00
coreplex diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
diplomacy diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
groundtest groundtest: fix test ram width 2017-06-20 18:11:22 -07:00
jtag jtag: make it easier to assign MFR ID externally 2017-04-14 01:03:11 -07:00
junctions debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
regmapper ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00
rocket rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
rocketchip diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
tile Move RoCC interface to Diplomacy and TL2 (#807) 2017-06-22 12:07:09 -07:00
uncore debug: Fix race between resumereq and resumeack 2017-06-29 12:27:23 -07:00
unittest unittest: balance the run times of the tests 2017-05-17 14:02:59 -07:00
util Add grouped method to AugmentedUInt, like Seq.grouped 2017-06-28 02:09:18 -07:00