7 Commits

Author	SHA1	Message	Date
Wesley W. Terpstra	03f2fe02ac	coreplex: support rational crossing to L2 (#534)	2017-01-27 17:09:43 -08:00
Henry Cook	307f938b88	[rocket] bugfix: fixes #517	2017-01-19 17:48:04 -08:00
Henry Cook	9a6634cd40	Add TLBuffers on the L1 backends and blind exit points (#513) ... * [coreplex] add TLBuffers on the exit points from the Tile and Coreplex * [config] WithBootROMFile	2017-01-17 11:57:23 -08:00
Henry Cook	74b6a8d02b	Refactor Tile to use cake pattern (#502) ... * [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests	2017-01-16 18:24:08 -08:00
Wesley W. Terpstra	b7963eca4e	copyright: ran scripts/modify-copyright	2016-11-27 22:15:43 -08:00
Wesley W. Terpstra	2b80386a9e	rocketchip: TileInterrupts needs a TLCacheEdge (#456)	2016-11-25 17:02:29 -08:00
Wesley W. Terpstra	c230580157	coreplex: rename RocketPlex => RocketTiles	2016-11-22 17:27:58 -08:00