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Shreesha SrinathandWesley W. Terpstra ff1f0170dc changing SystemVerilog params to Verilog style (#801) 
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
 2017-06-16 22:47:12 -07:00
Shreesha SrinathandGitHub 4059d9417f GeneratorUtils: support to elaborate a RawModule 2017-06-15 14:33:02 -07:00