riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,897 Commits 1 Branch 0 Tags 13 MiB
ea4b1bc349
Commit Graph

4897 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andrew Waterman
c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00
Andrew Waterman
3e72f9779f Handle single-step with a pipeline stall, not a flush 
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
 2017-04-05 19:52:44 -07:00
Megan Wachs
c5b0b6fb85 debug: bump openOCD version to pick up read_mem fix. Use MemTest64 instead because it's more likely to fail than SimpleS0Test 2017-04-05 15:14:32 -07:00
Megan Wachs
2601740542 debug: fix some typos related to the ID->SEL mapping functions 2017-04-05 15:14:32 -07:00
Megan Wachs
b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset 2017-04-05 15:14:32 -07:00
Megan Wachs
eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. 2017-04-05 15:14:32 -07:00
solomatnikov
127f121ef2 Preserve id_do_fence (#651) 2017-04-05 08:29:45 -07:00
Andrew Waterman
19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed 
This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
 2017-04-03 21:13:52 -07:00
Megan Wachs
629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
Megan Wachs
d2c1bdc2ce Debug Controls (#639) 
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
 2017-04-03 13:31:35 -07:00
Yunsup Lee
716533f77f Merge pull request #643 from ucb-bar/update-pmp-encoding 
bump riscv-tools
 2017-03-31 20:52:49 -07:00
Yunsup Lee
983a561720 bump riscv-tools 2017-03-31 19:20:08 -07:00
Andrew Waterman
410e9cf736 I$ bugfix, to be reworked 2017-03-31 12:17:41 -07:00
Henry Cook
9f371abf3b Merge pull request #638 from ucb-bar/riscv-tools-on-priv-1.10 
Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v0…
 2017-03-31 01:56:36 -07:00
Henry Cook
e92eaa7156 Merge branch 'master' into riscv-tools-on-priv-1.10 2017-03-30 22:31:29 -07:00
Henry Cook
e8f337e963 Merge pull request #636 from ucb-bar/name-rams 
Name L1$ RAMs consistently
 2017-03-30 22:30:12 -07:00
Megan Wachs
dec567ab0c Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v013 version. 2017-03-30 20:22:54 -07:00
Henry Cook
b9550e8523 Merge branch 'master' into name-rams 2017-03-30 17:36:01 -07:00
Henry Cook
b6da81a66c Merge pull request #624 from ucb-bar/debug_v013_pr 
Debug v013 [WIP]
 2017-03-30 17:35:26 -07:00
Andrew Waterman
a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman
2720095b8e Give D$ RAMs consistent names 2017-03-30 15:49:14 -07:00
Andrew Waterman
70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Henry Cook
bcaee9834c travis_wait 30 2017-03-30 13:22:33 -07:00
Megan Wachs
0828ebe911 debug_v013: bump fesvr to use autoexec feature for memory writes. 2017-03-30 11:46:28 -07:00
Megan Wachs
9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Schuyler Eldridge
c61714a465 Pass MODEL variable to emulator.cc 
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
 2017-03-30 02:08:01 -07:00
Andrew Waterman
fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra
a2fc51d65e soc: compatible with "simple-bus" => scanned for platform devices 2017-03-30 00:36:23 -07:00
Alex Solomatnikov
9f85b2e996 Do allow make to remove .vpd files on Ctrl-C 2017-03-30 00:36:23 -07:00
Andrew Waterman
3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman
8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman
25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Andrew Waterman
80fb002962 Don't use Vec as lvalue 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) 2017-03-29 23:07:17 -07:00
Megan Wachs
a14b7b5794 debug_v013: bump riscv-tools for slightly more efficient FESVR 2017-03-29 21:42:36 -07:00
Megan Wachs
24509fc69f debug_v013: Bump FESVR to pick up minor off-by-1 in error printing code. 2017-03-29 15:20:07 -07:00
Megan Wachs
d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Megan Wachs
f6e72a3ef6 debug: Bump riscv-tools to pick up FESVR to version that works with debug v013 2017-03-29 14:46:06 -07:00
Megan Wachs
375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) 2017-03-28 21:14:22 -07:00
Megan Wachs
ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR 2017-03-28 21:13:45 -07:00
Megan Wachs
ff38ebdf5e debug: Bump FESVR version to initial Debug v13. Doesn't work yet. 2017-03-28 21:12:57 -07:00
Andrew Waterman
8dfbf4532a Use 1 MHz as default timebase (#628) 
Defaulting to 0 prevents Linux from booting
 2017-03-28 19:59:56 -07:00
Andrew Waterman
44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew Waterman
db3ed12ce3 Fix regression in groundtest DummyPTW 
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
 2017-03-28 00:56:14 -07:00
Andrew Waterman
4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00