riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra
df44b23956 axi4: SRAM can emulate incompletely populated memory 2017-07-07 21:40:39 -07:00
Wesley W. Terpstra
b2cc4b99ed tilelink: TestSRAM reports errors on illegal access 2017-07-07 21:40:36 -07:00
Wesley W. Terpstra
e8cb6dafd3 tilelink: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
f1fb3be603 ahb: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
19851a7c9e apb: SRAM reports errors on illegal access 2017-07-07 21:15:33 -07:00
Wesley W. Terpstra
025f7d890b axi4: SRAM now reports errors on illegal address (#852) 2017-07-07 19:27:32 -07:00
Henry Cook
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Megan Wachs
c28c23150d Merge pull request #850 from freechipsproject/plic_undefZero 
PLIC: (undefZero=true) Don't allow addresses to alias
 2017-07-06 18:39:10 -07:00
Megan Wachs
76a1ae667f PLIC: (undefZero=true) Don't allow addresses to alias 
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
 2017-07-06 17:57:08 -07:00
Andrew Waterman
a0cbc376b4 Merge pull request #849 from freechipsproject/l2-tlb 
L1 memory system improvements
 2017-07-06 13:03:06 -07:00
Andrew Waterman
e1cc0a0a0e Mask debug interrupts similarly to other interrupts (#847) 
This makes single-step exceptions higher-priority than debug interrupts.
 2017-07-06 12:03:24 -07:00
Andrew Waterman
b2351c5fbf Use consistent casing 2017-07-06 11:16:56 -07:00
Andrew Waterman
be4eceec0d Fix stupid D$ probe bug 2017-07-06 01:20:47 -07:00
Andrew Waterman
90a7d6a343 Add L2 TLB option 2017-07-06 01:19:18 -07:00
Andrew Waterman
438abc76d2 Handle TL errors in L1 I$ 
Cache the error bit in the tag array; report precisely on access.
 2017-07-06 01:02:11 -07:00
Megan Wachs
988caf5e34 Merge pull request #848 from freechipsproject/revert-839-bump-firrtl 
Revert "Bump firrtl"
 2017-07-05 22:32:45 -07:00
Megan Wachs
029886d0d5 Revert "Bump firrtl" 2017-07-05 21:13:47 -07:00
Jack Koenig
f6880555df Merge pull request #839 from freechipsproject/bump-firrtl 
Bump firrtl
 2017-07-05 14:59:58 -07:00
Megan Wachs
734a178e4e Merge pull request #846 from freechipsproject/travis-delete-caches 
Update README_TRAVIS.md
 2017-07-05 13:52:26 -07:00
Megan Wachs
94262ea950 Update README_TRAVIS.md 
add some headers
 2017-07-05 11:45:04 -07:00
Megan Wachs
84c2bf5504 Update README_TRAVIS.md 
Clarify when to delete caches
 2017-07-05 11:40:36 -07:00
Jack Koenig
bb4452435f Bump Firrtl to get const prop registers and name improvements 2017-07-05 10:44:18 -07:00
Andrew Waterman
ec9fbe26d8 Merge pull request #843 from freechipsproject/tag-ecc 
Add tag ECC to D$
 2017-07-04 16:20:11 -07:00
Andrew Waterman
0ef45fac9b Add tag ECC to D$ 2017-07-03 18:16:37 -07:00
Andrew Waterman
e9752f76ae Improve probe state machine 
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
 2017-07-03 16:25:04 -07:00
Megan Wachs
85f37146d5 Merge pull request #842 from freechipsproject/fesvr-multi 
Bump FESVR for multi-core support
 2017-07-03 15:31:41 -07:00
Megan Wachs
ddd2b2236d bump riscv-tools/riscv-fesvr to pick up multicore fixes 2017-07-03 13:25:05 -07:00
Megan Wachs
3d28c0182d travis: add a branch whitelist with just 'master'. 
Travis allows us to build on branch updates and on PRs. Right now our process is to build always on PRs, but to manually only build 'master' when we know that riscv-tools has been bumped (because that rebuilds the master cache which holds riscv-tools). But this is an annoying and error-prone processes that requires extra admin permissions.

With this change, i think we can just leave "Build Branch Updates" to "ON" and get the same effect we are currently doing manually, because only on update to master branch will it do a build. PRs to master branch will get a build. PRs to other branches will I believe NOT get a build.
 2017-07-03 13:25:05 -07:00
Richard Xia
ee9789eb68 Merge pull request #840 from freechipsproject/fix-dcache-exception-assignment-order 
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
 2017-06-30 18:50:49 -07:00
Richard Xia
5b46350bc3 Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment. 2017-06-30 17:44:16 -07:00
Megan Wachs
69ab3626ca Merge pull request #837 from freechipsproject/plic_recode 
plic: Recode to use OH knowledge
 2017-06-30 16:05:32 -07:00
Megan Wachs
8c92c50d85 plic: make assertion comment right 2017-06-30 14:25:09 -07:00
Megan Wachs
f31ae008f3 plic: Clean up comments and simplify checking 2017-06-30 14:15:26 -07:00
Megan Wachs
76f8de75e3 plic: comment tidying 2017-06-30 12:51:09 -07:00
Megan Wachs
3da26b0aa8 plic: Add some assertions to check one-hot assumptions 2017-06-30 12:32:58 -07:00
Ben Keller
85ac8d588c Excise the last instance of run-bmarks-test (#836) 2017-06-30 11:50:40 -07:00
Megan Wachs
237689b799 Merge pull request #838 from freechipsproject/more_plic 
plic: Use same recoding technique on complete as well as claim
 2017-06-30 11:06:27 -07:00
Wesley W. Terpstra
367d4aebe6 Set complete unconditionally 2017-06-30 10:15:53 -07:00
Wesley W. Terpstra
4e9f65b2ef Simplify logic further and bugfix 
complete was being set unconditionally
 2017-06-30 10:07:39 -07:00
Megan Wachs
e8e709c941 plic: Use same recoding technique on complete as well as claim 2017-06-30 08:36:00 -07:00
Wesley W. Terpstra
3dca2bc4a3 gah 2017-06-30 01:07:29 -07:00
Wesley W. Terpstra
e43b7accf9 Fix compile error and eliminate wasteful wires 2017-06-30 01:06:02 -07:00
Megan Wachs
834bcf6b7e PLIC: simplify some scala code 2017-06-29 19:35:15 -07:00
Megan Wachs
eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. 2017-06-29 19:09:57 -07:00
Wesley W. Terpstra
e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
Megan Wachs
ae6971b6db Merge pull request #834 from freechipsproject/resumereq-race 
debug: Fix race between resumereq and resumeack
 2017-06-29 13:38:20 -07:00
Megan Wachs
0668f13d99 debug: Fix race between resumereq and resumeack 
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
 2017-06-29 12:27:23 -07:00
Wesley W. Terpstra
7dae3388e1 Merge pull request #830 from freechipsproject/flip-dts-idtim 
Flip dts itim and dtim references
 2017-06-29 00:18:19 -07:00
Wesley W. Terpstra
5edc4546e3 rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
Wesley W. Terpstra
7d6f8d48f2 Revert "rocket: link dtim to its cpu" 
This reverts commit e6c2d446cc.
 2017-06-28 23:10:57 -07:00