9 Commits

Author	SHA1	Message	Date
Henry Cook	b86f4b9bb7	config: use Field defaults over Config defaults ... Also rename some keys that had the same class name as their value's class name.	2017-09-13 11:25:42 -07:00
Wesley W. Terpstra	5886025b1a	sbus => pbus: 2 buffers should already be enough ... There is a buffer on the sbus backside. There is a buffer on the pbus frontside. Between them is only an AtomicAutomata. That should be enough for most designs.	2017-09-05 15:03:38 -07:00
Henry Cook	a902e15987	pbus: clarify that we are adding buffers when attaching to sbus	2017-09-05 15:03:38 -07:00
Megan Wachs	94f06dc85c	pbus: turn down overkill buffering between PBus and SBus	2017-09-05 15:03:38 -07:00
Henry Cook	3bde9506c6	coreplex: allow buffer chains on certain bus ports	2017-09-05 15:03:36 -07:00
Megan Wachs	c99afe4c66	buses: Name all the things.	2017-08-30 17:31:42 -07:00
Henry Cook	2910d6fa2a	tilelink: make bus xbar protected so it can be suggestNamed	2017-08-07 17:30:24 -07:00
Yunsup Lee	c9e467a668	coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887)	2017-07-25 00:55:55 -07:00
Henry Cook	01ca3efc2b	Combine Coreplex and System Module Hierarchies (#875) ... * coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC	2017-07-23 08:31:04 -07:00