7 Commits

Include renames

Author	SHA1	Message	Date
Yunsup Lee	d6df479870	move 'include /Makefrag' out of top-level Makefrag	2015-07-14 16:13:32 -07:00
Yunsup Lee	221007595b	allow BACKEND/CONFIG be environment variables	2014-09-17 11:12:08 -07:00
Yunsup Lee	275b72368b	add CONFIG to the name of simulator executable	2014-09-11 22:11:58 -07:00
Yunsup Lee	ddfd3ce968	further generalize fpga/vlsi builds	2014-09-08 00:21:57 -07:00
Yunsup Lee	763c57931b	fix problem introduced with verilog generation in vsim/fsim	2014-09-04 09:49:57 -07:00
Scott Beamer	6c6f5a3843	add verilog target to build without simulator	2014-09-03 17:28:45 -07:00
Yunsup Lee	c03c09ec31	update for rocket-chip release	2014-08-31 20:26:55 -07:00