riscv/rocket-chip
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d5c6494f59
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51 Commits

Author SHA1 Message Date
Wesley W. Terpstra
d5c6494f59 tilelink: Bus.toRationalSlaves can have a BufferChain 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80965e8230 tilelink Buffer: use new :=? adapter API 2017-09-07 16:03:35 -07:00
Megan Wachs
dcafb5fea3 Merge remote-tracking branch 'origin/master' into async_reg 2017-09-06 11:07:19 -07:00
Megan Wachs
667d966410 TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming 2017-09-05 15:03:38 -07:00
Megan Wachs
c353f68dc0 buses: name dummy buffers too 2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Megan Wachs
c99afe4c66 buses: Name all the things. 2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00
Megan Wachs
a62ce0afe6 TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer. 2017-08-29 10:36:46 -07:00
Megan Wachs
130b24355f syncregs: Use synchronizer primitives for IntXing 2017-08-24 17:39:07 -07:00
Wesley W. Terpstra
f191bb994c PatternPusher: can now expect a certain output (#952) 2017-08-11 18:10:27 -07:00
Wesley W. Terpstra
baf769f924 tilelink: add PatternPusher, a device to inject a fixed traffic pattern (#950) 2017-08-11 15:07:10 -07:00
Henry Cook
c8f8806df0 Merge pull request #932 from freechipsproject/tl-bus-delayer 
tilelink: allow insertion of TLDelayer on TLBus outward node
 2017-08-07 19:01:39 -07:00
Henry Cook
c4092dd0cc tilelink: improve entropy of bus delayer 2017-08-07 17:36:07 -07:00
Henry Cook
2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed 2017-08-07 17:30:24 -07:00
Henry Cook
c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
Wesley W. Terpstra
f8b45564d1 tilelink: RAMModel must support source reuse 
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
 2017-08-07 16:01:15 -07:00
Megan Wachs
50c85f1b62 TLXbar: Allow more masters and slaves and issue a warning. 2017-08-03 15:46:06 -07:00
Megan Wachs
595415d207 TLFuzzer: Correct the number of ordered clients created 2017-08-02 15:48:21 -07:00
Megan Wachs
fc5c04ed4b TLFuzzer: Allow Ordered clients to be created as well by the fuzzer 2017-08-02 14:44:18 -07:00
Wesley W. Terpstra
d7fd9d2b82 tilelink: Filter, add another case 2017-07-31 16:51:26 -07:00
Wesley W. Terpstra
b126105230 tilelink: add TLMap to make it possible to move slaves 2017-07-31 16:39:00 -07:00
Wesley W. Terpstra
13d3ffbcaa tilelink: Filter now support arbitrary filter functions 2017-07-31 16:38:38 -07:00
Wesley W. Terpstra
a0db929003 tilelink: use the Monitor to enforce Probe sourcing 2017-07-28 18:08:00 -07:00
Wesley W. Terpstra
9a36755b6a tilelink: CacheCork uses constructor helpers 2017-07-27 18:38:15 -07:00
Wesley W. Terpstra
45189c3e30 tilelink: CacheCork now supports errors and BtoT upgrade 
- Acquire.BtoT succeeds with toT instantly
- AccessAckData.error causes Grant.toN.error
 2017-07-27 18:38:13 -07:00
Wesley W. Terpstra
651da73d89 tilelink: it is now legal to support Acquire for UNCACHED regions 
These cases exist:
  GET_EFFECTS, PUT_EFFECTS, UNCACHEABLE && !supportsAcquire: MMIO
  UNCACHED && !supportsAcquire: speculation ok and may be cached
  UNCACHED && supportsAcquire: LLC/CacheCork applied (slave never probes)
  CACHED, TRACKED && supportsAcquire: slave might probe
 2017-07-27 11:11:22 -07:00
Wesley W. Terpstra
0ab5cb67b3 tilelink: fix RAMModel handling of AMOs on early source reuse (#897) 2017-07-27 11:07:13 -07:00
Wesley W. Terpstra
9804bdc34e tilelink: remove obsolete addr_lo signal (#895) 
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
 2017-07-26 16:01:21 -07:00
Wesley W. Terpstra
d096d5d1c4 tilelink: fix AtomicAutomata bug wrt early source reuse 
The new fuzzer already found it's first victim.
 2017-07-26 12:52:29 -07:00
Wesley W. Terpstra
6550ae2e31 tilelink: increase Fuzzer source reuse aggression 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
1efdca106c tilelink: RAMModel support early reuse of source 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
138276fd87 tilelink: SourceShrinker should work also for 0 latency 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra
b2edca2a6b tilelink: cut WidthWidget from dependency on addr_lo 2017-07-26 10:31:09 -07:00
Wesley W. Terpstra
ede87c1f73 tilelink: rewrite WidthWidget beat splitter 
- split the data based on the address, not the mask
  (the first version of TileLink did not have low address bits)
- the dependency on addr_lo is now exposed and easy to replace
 2017-07-26 10:24:16 -07:00
Wesley W. Terpstra
0f5065fbf3 tilelink: WidthWidget rewrite beat merging 
- errors are properly OR reduced
- registers latched only as needed (was previously a shift register)
- combines beats without inspecting address (removes addr_lo dependency)
 2017-07-26 10:24:12 -07:00
Wesley W. Terpstra
f0ffb7e31e tilelink: initialize toggle in Fragmenter (#894) 
No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
 2017-07-26 10:21:31 -07:00
Wesley W. Terpstra
c2b8b08461 tilelink: fix Fragmenter source re-use bug (#888) 
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.

However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.

To solve this, we alternate an a.source bit every time D completes a txn.
 2017-07-25 16:23:55 -07:00
Wesley W. Terpstra
68ed055f6d chiplink: adjust bus view to include the splitter (#886) 2017-07-24 21:41:17 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
 2017-07-23 08:31:04 -07:00
Megan Wachs
f2002839eb TLFragmenter: Continuing my spot battles on requires without explanatory strings (#882) 2017-07-21 21:55:32 -07:00
Yunsup Lee
21954c1c73 tileink: FIFOFixer should cope with zero-latency devices 2017-07-19 19:38:27 -07:00
Wesley W. Terpstra
416629b3bf tilelink: FIFOFixer should fix no domain => domain cases (#873) 2017-07-17 22:32:17 -07:00
Wesley W. Terpstra
fc75ada577 tilelink: Monitor should report line numbers of connection that failed (#872) 2017-07-17 21:29:14 -07:00
Howard Mao
ec57994784 fix the TLFuzzer IO (#869) 2017-07-17 14:59:35 -07:00
Wesley W. Terpstra
16e8709144 tilelink: it is now legal to have errors on {Release,Hint}Ack (#864) 2017-07-14 16:13:30 -07:00
Wesley W. Terpstra
b7f1ba3428 tilelink: FIFOFixer must support null cases (#860) 
In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
 2017-07-12 22:20:31 -07:00
Wesley W. Terpstra
09b9d33a9a tilelink: FIFOFixer now has a policy parameter 2017-07-12 17:38:55 -07:00
Wesley W. Terpstra
702143eb33 tilelink: SRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
e8cb6dafd3 tilelink: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00