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Arbiter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AsyncCrossing.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AtomicAutomata.scala
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tilelink: fix AtomicAutomata bug wrt early source reuse
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2017-07-26 12:52:29 -07:00 |
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Atomics.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Broadcast.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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Buffer.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Bundles.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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Bus.scala
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chiplink: adjust bus view to include the splitter (#886)
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2017-07-24 21:41:17 -07:00 |
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CacheCork.scala
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tilelink: CacheCork now supports errors and BtoT upgrade
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2017-07-27 18:38:13 -07:00 |
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Delayer.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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Edges.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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Example.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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FIFOFixer.scala
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tileink: FIFOFixer should cope with zero-latency devices
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2017-07-19 19:38:27 -07:00 |
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Filter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Fragmenter.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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Fuzzer.scala
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tilelink: increase Fuzzer source reuse aggression
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2017-07-26 12:37:31 -07:00 |
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HintHandler.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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IntNodes.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Isolation.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Metadata.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Monitor.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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NodeNumberer.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Nodes.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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package.scala
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Combine Coreplex and System Module Hierarchies (#875)
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2017-07-23 08:31:04 -07:00 |
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Parameters.scala
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tilelink: it is now legal to support Acquire for UNCACHED regions
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2017-07-27 11:11:22 -07:00 |
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RAMModel.scala
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tilelink: fix RAMModel handling of AMOs on early source reuse (#897)
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2017-07-27 11:07:13 -07:00 |
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RationalCrossing.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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RegisterRouter.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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RegisterRouterTest.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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SourceShrinker.scala
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tilelink: SourceShrinker should work also for 0 latency
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2017-07-26 12:37:31 -07:00 |
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Splitter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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SRAM.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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ToAHB.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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ToAPB.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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ToAXI4.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
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WidthWidget.scala
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tilelink: cut WidthWidget from dependency on addr_lo
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2017-07-26 10:31:09 -07:00 |
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Xbar.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
