riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,628 Commits 1 Branch 0 Tags
bf431c0a53fb7eb61c7f2fe47c5004f8a49f136c
Commit Graph
1 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Shreesha SrinathandWesley W. Terpstra ff1f0170dc changing SystemVerilog params to Verilog style (#801) 
vivado-2016.1 synthesis doesn't support SystemVerilog string type parameters
 2017-06-16 22:47:12 -07:00