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riscv/rocket-chip
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5,518 Commits 1 Branch 0 Tags
bb1976552f690ebcd588d4d947559ec80906aa88
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6 Commits
Author SHA1 Message Date
Andrew Waterman dbf599f6a1 Support SynchronizerShiftReg(sync = 0)
This makes it easier to parameterize code where the synchronizer
might not always be needed.
2017-09-20 00:05:07 -07:00
Megan Wachs 126d56b254 synchronizers: I learn how foldRight works 2017-09-07 10:48:27 -07:00
Megan Wachs 1da6cb85ab shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created. 2017-09-07 09:57:50 -07:00
Megan Wachs 3c4b472f66 shift regs: remove some unnecessary primitives, and add some that actually are necessary 2017-09-06 10:37:59 -07:00
Megan Wachs 777f052f95 regs: Add named/initial value ShiftRegister primitives so they are all in one place 2017-09-05 17:32:53 -07:00
Megan Wachs e9e46db600 sync reg: Rename the file to reflect the more generic shift registers also in the file. 2017-09-05 15:54:25 -07:00
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