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riscv/rocket-chip
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135 Commits 1 Branch 0 Tags
b42e140e05f953e53c7499a2a7ff7e4dc5b7758b
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Author SHA1 Message Date
Stephen Twigg 6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Stephen Twigg f27c0fb010 Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2 2013-09-05 15:01:56 -07:00
Stephen Twigg 69daae0dae Add dependency resolvers to build.scala to fix build script 2013-09-05 14:56:41 -07:00
Stephen Twigg c1b1a21a0f If +stats is set when running simv-debug, will only output vcd data when cr28 is high. 2013-07-30 16:39:47 -07:00
Stephen Twigg 3f874342a4 Update chisel to appropriate version for reference chip build. 2013-07-10 17:08:56 -07:00
Stephen Twigg bd43ca8423 Merge branch 'master' of github.com:ucb-bar/reference-chip 2013-05-23 17:51:24 -07:00
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