Jack Koenig
588dacec17
Bump Chisel and Firrtl ( #1134 )
2017-12-08 14:22:18 -08:00
Megan Wachs
f86489b59e
JTAG: Use sorted map for stability ( #1073 )
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* JTAG: Use sorted map for stability
Otherwise the generated FIRRTL/Verilog is non deterministic
* jtag : parens for clarity
* jtag: Use deterministic ListMap and sort for stability
* JTAG: use slightly clearer SortedMap (clearer to me anyway)
* jtag: whitespace cleanup
2017-10-31 15:33:41 -07:00
Megan Wachs
a8ab06d572
JTAG: Add coverage points to the JTAG Tap
2017-10-02 11:08:13 -07:00
Jim Lawson
f1b7666d21
Jtagresettobool - add explicit toBool cast now required on reset. ( #984 )
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Add explicit toBool cast on reset, for chisel3 compatability
2017-09-06 09:49:47 -07:00
Jim Lawson
2bf91a0558
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Megan Wachs
fd7f4a4c0f
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
Megan Wachs
8e6beb80be
Add ucb-art/chisel-jtag ( #612 )
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* jtag: Add ucb-art/chisel-jtag to junctions.
* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch
* jtag: move to a top-level package
2017-03-26 18:03:21 -07:00