242 lines
9.0 KiB
Scala
242 lines
9.0 KiB
Scala
// See LICENSE.jtag for license details.
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package jtag
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import chisel3._
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import chisel3.util._
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/** JTAG signals, viewed from the master side
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*/
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class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
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val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None
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val TCK = Clock(OUTPUT)
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val TMS = Output(Bool())
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val TDI = Output(Bool())
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val TDO = Input(new Tristate())
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override def cloneType = new JTAGIO(hasTRSTn).asInstanceOf[this.type]
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}
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/** JTAG block output signals.
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*/
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class JtagOutput(irLength: Int) extends Bundle {
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val state = Output(JtagState.State.chiselType()) // state, transitions on TCK rising edge
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val instruction = Output(UInt(irLength.W)) // current active instruction
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val reset = Output(Bool()) // synchronous reset asserted in Test-Logic-Reset state, should NOT hold the FSM in reset
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override def cloneType = new JtagOutput(irLength).asInstanceOf[this.type]
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}
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class JtagControl extends Bundle {
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val jtag_reset = Input(Bool())
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}
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/** Aggregate JTAG block IO.
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*/
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class JtagBlockIO(irLength: Int) extends Bundle {
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val jtag = Flipped(new JTAGIO())
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val control = new JtagControl
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val output = new JtagOutput(irLength)
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override def cloneType = new JtagBlockIO(irLength).asInstanceOf[this.type]
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}
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/** Internal controller block IO with data shift outputs.
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*/
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class JtagControllerIO(irLength: Int) extends JtagBlockIO(irLength) {
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val dataChainOut = Output(new ShifterIO)
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val dataChainIn = Input(new ShifterIO)
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override def cloneType = new JtagControllerIO(irLength).asInstanceOf[this.type]
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}
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/** JTAG TAP controller internal block, responsible for instruction decode and data register chain
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* control signal generation.
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*
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* Misc notes:
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* - Figure 6-3 and 6-4 provides examples with timing behavior
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*/
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class JtagTapController(irLength: Int, initialInstruction: BigInt) extends Module {
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require(irLength >= 2) // 7.1.1a
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val io = IO(new JtagControllerIO(irLength))
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val tdo = Wire(Bool()) // 4.4.1c TDI should appear here uninverted after shifting
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val tdo_driven = Wire(Bool())
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io.jtag.TDO.data := NegativeEdgeLatch(clock, tdo, name = Some("tdoReg")) // 4.5.1a TDO changes on falling edge of TCK, 6.1.2.1d driver active on first TCK falling edge in ShiftIR and ShiftDR states
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io.jtag.TDO.driven := NegativeEdgeLatch(clock, tdo_driven, name = Some("tdoeReg"))
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//
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// JTAG state machine
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//
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val stateMachine = Module(new JtagStateMachine)
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stateMachine.io.tms := io.jtag.TMS
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val currState = stateMachine.io.currState
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io.output.state := stateMachine.io.currState
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// At this point, the TRSTn should already have been
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// combined with any POR, and it should also be
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// synchronized to TCK.
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require(!io.jtag.TRSTn.isDefined, "TRSTn should be absorbed into jtckPOReset outside of JtagTapController.")
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stateMachine.io.jtag_reset := io.control.jtag_reset
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//
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// Instruction Register
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//
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// 7.1.1d IR shifter two LSBs must be b01 pattern
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// TODO: 7.1.1d allow design-specific IR bits, 7.1.1e (rec) should be a fixed pattern
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// 7.2.1a behavior of instruction register and shifters
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val irChain = Module(CaptureUpdateChain(UInt(irLength.W)))
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irChain.suggestName("irChain")
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irChain.io.chainIn.shift := currState === JtagState.ShiftIR.U
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irChain.io.chainIn.data := io.jtag.TDI
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irChain.io.chainIn.capture := currState === JtagState.CaptureIR.U
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irChain.io.chainIn.update := currState === JtagState.UpdateIR.U
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irChain.io.capture.bits := "b01".U
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val updateInstruction = Wire(Bool())
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val nextActiveInstruction = Wire(UInt(irLength.W))
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val activeInstruction = NegativeEdgeLatch(clock, nextActiveInstruction, updateInstruction, name = Some("irReg")) // 7.2.1d active instruction output latches on TCK falling edge
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when (reset) {
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nextActiveInstruction := initialInstruction.U(irLength.W)
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updateInstruction := true.B
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} .elsewhen (currState === JtagState.UpdateIR.U) {
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nextActiveInstruction := irChain.io.update.bits
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updateInstruction := true.B
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} .otherwise {
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updateInstruction := false.B
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}
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io.output.instruction := activeInstruction
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io.output.reset := currState === JtagState.TestLogicReset.U
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//
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// Data Register
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//
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io.dataChainOut.shift := currState === JtagState.ShiftDR.U
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io.dataChainOut.data := io.jtag.TDI
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io.dataChainOut.capture := currState === JtagState.CaptureDR.U
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io.dataChainOut.update := currState === JtagState.UpdateDR.U
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//
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// Output Control
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//
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when (currState === JtagState.ShiftDR.U) {
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tdo := io.dataChainIn.data
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tdo_driven := true.B
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} .elsewhen (currState === JtagState.ShiftIR.U) {
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tdo := irChain.io.chainOut.data
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tdo_driven := true.B
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} .otherwise {
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tdo_driven := false.B
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}
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}
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object JtagTapGenerator {
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/** JTAG TAP generator, enclosed module must be clocked from TCK and reset from output of this
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* block.
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*
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* @param irLength length, in bits, of instruction register, must be at least 2
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* @param instructions map of instruction codes to data register chains that select that data
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* register; multiple instructions may map to the same data chain
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* @param idcode optional idcode, tuple of (instruction code, idcode)
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*
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* @note all other instruction codes (not part of instructions or idcode) map to BYPASS
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* @note initial instruction is idcode (if supported), otherwise all ones BYPASS
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*
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* Usage notes:
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* - 4.3.1b TMS must appear high when undriven
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* - 4.3.1c (rec) minimize load presented by TMS
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* - 4.4.1b TDI must appear high when undriven
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* - 4.5.1b TDO must be inactive except when shifting data (undriven? 6.1.2)
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* - 6.1.3.1b TAP controller must not be (re-?)initialized by system reset (allows
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* boundary-scan testing of reset pin)
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* - 6.1 TAP controller can be initialized by a on-chip power on reset generator, the same one
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* that would initialize system logic
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*
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* TODO:
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* - support concatenated scan chains
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*/
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def apply(irLength: Int, instructions: Map[BigInt, Chain], idcode:Option[(BigInt, BigInt)]=None): JtagBlockIO = {
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// Create IDCODE chain if needed
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val allInstructions = idcode match {
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case Some((icode, idcode)) => {
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val idcodeChain = Module(CaptureChain(UInt(32.W)))
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idcodeChain.suggestName("idcodeChain")
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require(idcode % 2 == 1, "LSB must be set in IDCODE, see 12.1.1d")
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require(((idcode >> 1) & ((1 << 11) - 1)) != JtagIdcode.dummyMfrId, "IDCODE must not have 0b00001111111 as manufacturer identity, see 12.2.1b")
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require(!(instructions contains icode), "instructions may not contain IDCODE")
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idcodeChain.io.capture.bits := idcode.U(32.W)
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instructions + (icode -> idcodeChain)
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} case None => instructions
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}
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val bypassIcode = (BigInt(1) << irLength) - 1 // required BYPASS instruction
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val initialInstruction = idcode match { // 7.2.1e load IDCODE or BYPASS instruction after entry into TestLogicReset
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case Some((icode, _)) => icode
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case None => bypassIcode
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}
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require(!(allInstructions contains bypassIcode), "instructions may not contain BYPASS code")
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val controllerInternal = Module(new JtagTapController(irLength, initialInstruction))
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val unusedChainOut = Wire(new ShifterIO) // De-selected chain output
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unusedChainOut.shift := false.B
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unusedChainOut.data := false.B
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unusedChainOut.capture := false.B
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unusedChainOut.update := false.B
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val bypassChain = Module(JtagBypassChain())
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// The Great Data Register Chain Mux
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bypassChain.io.chainIn := controllerInternal.io.dataChainOut // for simplicity, doesn't visibly affect anything else
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require(allInstructions.size > 0, "Seriously? JTAG TAP with no instructions?")
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val chainToIcode = allInstructions groupBy { case (icode, chain) => chain } map {
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case (chain, icodeToChain) => chain -> icodeToChain.keys
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}
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val chainToSelect = chainToIcode map {
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case (chain, icodes) => {
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assume(icodes.size > 0)
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val icodeSelects = icodes map { controllerInternal.io.output.instruction === _.asUInt(irLength.W) }
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chain -> icodeSelects.reduceLeft(_||_)
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}
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}
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def foldOutSelect(res: WhenContext, x: (Chain, Bool)): WhenContext = {
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val (chain, select) = x
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// Continue the WhenContext with if this chain is selected
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res.elsewhen(select) {
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controllerInternal.io.dataChainIn := chain.io.chainOut
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}
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}
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val emptyWhen = when (false.B) { } // Empty WhenContext to start things off
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chainToSelect.toSeq.foldLeft(emptyWhen)(foldOutSelect).otherwise {
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controllerInternal.io.dataChainIn := bypassChain.io.chainOut
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}
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def mapInSelect(x: (Chain, Bool)) {
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val (chain, select) = x
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when (select) {
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chain.io.chainIn := controllerInternal.io.dataChainOut
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} .otherwise {
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chain.io.chainIn := unusedChainOut
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}
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}
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chainToSelect.map(mapInSelect)
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val internalIo = Wire(new JtagBlockIO(irLength))
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controllerInternal.io.jtag <> internalIo.jtag
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controllerInternal.io.control <> internalIo.control
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controllerInternal.io.output <> internalIo.output
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internalIo
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}
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}
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