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riscv/rocket-chip
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4,270 Commits 1 Branch 0 Tags
9de06f8c8369990936721764a890549f9346403e
Commit Graph
157 Commits
Author SHA1 Message Date
Andrew Waterman f4524e4c91 Add PML for Boolean.option; use it 2016-08-31 13:43:04 -07:00
Andrew Waterman 8dbee2b133 Don't conditionalize running bmarks on UseVM 2016-08-29 13:43:29 -07:00
Andrew Waterman f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
Andrew Waterman 9ca82dd397 reset default MulDiv config to moderately fast default
Closes #228.

In commit 3f8c60bbd6 I inadvertently
changed the configuration while refactoring it.
2016-08-29 12:31:52 -07:00
Henry CookandGitHub 93c801f598 Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227) 2016-08-25 17:26:28 -07:00
mwachs5andAndrew Waterman 22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) 2016-08-19 22:51:49 -07:00
Howard Mao 7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
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