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Commit Graph

9 Commits

Author SHA1 Message Date
Howard Mao
ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket 2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67 Move a bunch more things into util package
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Andrew Waterman
d0572d6aab Allow reset vector to be set dynamically
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins.  Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.

Additionally, allow MTVEC to *not* be reset.  In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does.  So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
Andrew Waterman
5566bf1b13 Don't route PLIC interrupts through PRCI
The PLIC is local to the Coreplex, and PRCI should not be.
2016-09-14 11:01:05 -07:00
Andrew Waterman
beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Andrew Waterman
9fea4c83da Add RV32F support 2016-09-07 00:05:39 -07:00
Andrew Waterman
f91552a650 Add performance counter support 2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c Update breakpoints to match @timsifive's debug spec 2016-08-29 12:31:52 -07:00
Howard Mao
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00