This is a follow-up to PR #1108.
Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.
* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard
If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
Fragmenter: add a third case for earlyAck (PutFulls only)
It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).
Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
If the PutFull was below the granularity, it was a single beat.
If the PutFull was multi-beat, it exceeds the granularity.
Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
* tilelink: ToAXI4 should format it's error message
* WithStatelessBridge: mark the memory bus incoherent and cacheable
... and hope that the user doesn't put more than one master down.
From the AHB spec:
"A slave only has to provide valid data when a transfer completes with an OKAY
response. ERROR responses do not require valid read data."
This makes it possible to treat chained composition associatively.
x := y :=? z :=* a ...
It also makes it easy to chain multiple optional adapters:
node :=? (Seq(a, b) ++ c ++ d)
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.
Instead of calling it Overwrite, we decided to split the Acquire type.
If you AcquirePerm, you MUST Release and ProbeAck with Data.
* CacheCork: an error Grant still says 'toT' even though it is transient
Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.
This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.
* Error: handle permissions properly
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.
Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
