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Commit Graph

117 Commits

Author SHA1 Message Date
Wesley W. Terpstra
fbbfc9c096 diplomacy: include edge type in inward/outward node handles
This is necessary capture the node implementation in the handle,
which is in turn necessary to support cloning a Node.
2017-12-01 11:26:58 -08:00
Wesley W. Terpstra
61ef560c75
tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111) 2017-11-14 17:49:10 -08:00
Wesley W. Terpstra
8b79f0394e
Merge pull request #1105 from freechipsproject/axi4-xbar
axi4: add an Xbar
2017-11-14 16:18:23 -08:00
Wesley W. Terpstra
509a48c9c9
TLToAXI4: block TL early source re-use before it goes to AXI4 (#1110)
This is a follow-up to PR #1108.

Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.
2017-11-14 16:08:43 -08:00
Wesley W. Terpstra
1902ba063a Filter: can claim to be out-of-order when you are not 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
353ddffc11 RAMModel: add a convenience object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
147fad6387
Fix AXI4 FIFO ordering for masters with early source reuse (#1108)
* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard

If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
2017-11-13 20:32:09 -08:00
Wesley W. Terpstra
b59880fe8e
Fragmenter: add an option for earlyAck only on PutFulls (#1095)
Fragmenter: add a third case for earlyAck (PutFulls only)

It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).

Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
  If the PutFull was below the granularity, it was a single beat.
  If the PutFull was multi-beat, it exceeds the granularity.

Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
2017-11-08 15:31:19 -08:00
Wesley W. Terpstra
7cc7cd5992 tilelink: AtomicAutomata; add errors to the unit test 2017-11-06 12:05:44 -08:00
Wesley W. Terpstra
88234ead0d tilelink: generalize ErrorEvaluator to more than just address patterns 2017-11-06 11:53:09 -08:00
Wesley W. Terpstra
25ea7fa852 tilelink: AtomicAutomata should OR the Get error with the Put error 2017-11-06 11:31:23 -08:00
Wesley W. Terpstra
16116991e7
Fix stateless caching (#1084)
* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.
2017-11-01 11:05:56 -07:00
Wesley W. Terpstra
4ccdbecb63
Async covers (#1085)
* cover: support covering cross-product of ready-valid

* tilelink: AsyncCrossing now has covers for all flow control logic
2017-11-01 11:03:45 -07:00
Wesley W. Terpstra
84145959e1
tilelink: fix error fragmentation from multibeat to multibeat (#1082)
Unfortunately, dLast is not actually correct for AccessAckData.
dFragnum is 0 for all the subbeats in the multibeat=>multibeat case.
2017-10-31 17:34:46 -07:00
Wesley W. Terpstra
45a904b396 ahb: ignore hrdata on an AHB error
From the AHB spec:
 "A slave only has to provide valid data when a transfer completes with an OKAY
  response. ERROR responses do not require valid read data."
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
e8ed450f13 unit tests: do not use LFSR16 which has a common seed!
We want each LFSR to generate independent noise.
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
0280a1f218 tilelink: add the ErrorEvaluator, a test bench error helper 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
2d12ddb4ed tilelink: ToAXI4 makes R channel errors sticky 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
d6f1612812 tilelink: ToAHB should make read errors sticky as well 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
4c9d9c6331 tilelink: optimize WidthWidget error circuit to nothing 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
0992a459be tilelink: Fragmenter should combine errors 2017-10-30 21:09:42 -07:00
Wesley W. Terpstra
13d0bf6808 tilelink: Monitor now enforces spec-defined error rules 2017-10-30 11:27:07 -07:00
Wesley W. Terpstra
a954f020a9 diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
6aac658184 diplomacy: convert all helper objects to return nodes 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
41705808dd Bus: remove deprecated crossing attach methods 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
7cf5d4aa90 diplomacy: define only primary node types 2017-10-28 11:16:56 -07:00
Wesley W. Terpstra
da7703aee9 crossings: deprecate non-island crossing style 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
76df1397e0 crossings: stop using deprecated APIs in tests 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
05d48d1807 TLBuffer: replace TLBufferChain with TLBuffer.chain 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
8c5e8dd071 coreplex: leverage improved := composition 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
e894d64bca diplomacy: support := composition
This makes it possible to treat chained composition associatively.
x := y :=? z :=* a ...

It also makes it easy to chain multiple optional adapters:
node :=? (Seq(a, b) ++ c ++ d)
2017-10-26 13:04:32 -07:00
Henry Cook
95a2e6ef27 coreplex: improve tile attachment adapters 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
c6f95570df IntNodes: moved from tilelink to their own package 2017-10-25 16:56:51 -07:00
Richard Xia
5a951799aa Add atomics support to DTS JSON file. 2017-10-18 15:17:53 -07:00
Henry Cook
1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable
tilelink: cacheable resource permission
2017-10-12 17:49:49 -07:00
Wesley W. Terpstra
8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051)
We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
2017-10-12 16:41:54 -07:00
Henry Cook
ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so 2017-10-12 13:49:40 -07:00
Henry Cook
66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry Cook
329a5c35d4 tilelink: unsafe cache cork discards outer d.sink 2017-10-11 00:30:51 -07:00
Henry Cook
1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Henry Cook
37406706b4 coreplex: move CacheCork in front of SBus
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
2017-10-10 16:24:32 -07:00
Wesley W. Terpstra
bd045a3b95 tilelink: split Acquire into Acquire{Block,Perm} (#1030)
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.

Instead of calling it Overwrite, we decided to split the Acquire type.

If you AcquirePerm, you MUST Release and ProbeAck with Data.
2017-10-05 12:49:49 -07:00
Wesley W. Terpstra
a2dc13669a Error grants (#1025)
* CacheCork: an error Grant still says 'toT' even though it is transient

Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.

This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.

* Error: handle permissions properly
2017-10-02 14:49:25 -07:00
Henry Cook
547bdc2b5b diplomacy: standardize sram device resource naming (#1022) 2017-09-29 14:52:26 -07:00
Wesley W. Terpstra
ce01ab2700 RegisterRouter: correctly create interrupts vector 2017-09-27 12:27:16 -07:00
Wesley W. Terpstra
31a934bec0 coreplex: buses are now LazyModules with LazyScope 2017-09-26 14:58:56 -07:00
Wesley W. Terpstra
a27e853101 diplomacy: move rendering properties to edges
FlipRendering { implicit p => ... } now changes the render direction of edges.
diplomatic NodeImps can specify a default render flip using the new 'render' method.
2017-09-26 13:24:36 -07:00
Wesley W. Terpstra
76c2aa1661 diplomacy: introduce the typing-saving SimpleNodeImp 2017-09-26 12:28:59 -07:00
Wesley W. Terpstra
60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra
bc225a4e82 diplomacy: place Monitors inside LazyModules sinks
We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.

Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
2017-09-22 23:36:17 -07:00